It can be appreciated that semiconductor processing can comprise hundreds of steps, during which many copies of an integrated circuit can be formed on a single semiconductor substrate or workpiece, generally known as a wafer. Generally, such processes involve creating several layers on and in the substrate that ultimately form a complete integrated circuit. This layering process can create electrically active regions in and on the semiconductor wafer surface. In a metal-oxide-semiconductor (MOS) transistor, for example, a gate structure is created, which can be energized to establish an electric field within a semiconductor channel, by which current is enabled to flow between a source region and a drain region within the transistor. The source and drain regions facilitate this conductance by virtue of containing a majority of hole (p type) or electron (n type) carriers.
It can also be appreciated that there is an ongoing desire to streamline fabrication processes to reduce fabrication times and cut costs. Likewise, it is desirable to enhance transistor operation. Accordingly, techniques that allow MOS transistors to be fabricated in a cost effective manner, while also improving the functionality of resulting transistors are desirable.